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SP6330, SP6332 and SP6334 Quad Power Supervisory Circuits with Manual Reset & Watchdog
FEATURES Low operating voltage of 1.6V Low operating current of 20A typical Monitors up to four supplies simultaneously Adjustable inputs monitor down to 0.5V Reset asserted down to 0.9V 2% accuracy over temperature range Open Drain (OD) or CMOS RSTB output or CMOS RST output 4 Reset Timeout Periods: 50ms, 100ms, 200ms and 400ms Watch Dog Input Functionality -- WDI Manual Reset Input (Active Low) -- MRIB 8 Pin TSOT package
V1 V2 MRIB
1 2 3 8 RSTB 7 WDI 6 GND 5
SP6330 8 Pin TSOT
V3 4
V4
Open Drain RESET
SEE PAGE 2 FOR OTHER AVAILABLE PINOUTS
Available in Lead Free Packaging DESCRIPTION
SP6330-SP6332- SP6334 Quad Power Supervisory Circuit Family is a family of microprocessor reset supervisory circuits with multiple reset voltages. The family provides low voltage monitoring ability for up-to four supplies with two precision factory-set thresholds and two user defined custom thresholds. These circuits perform a single function: if any of the input supply voltages drops below its associated threshold, reset outputs are asserted. The SP6330, SP6332, and SP6334 are packaged in an 8-pin TSOT package. All devices are fully specified over -40oC to +85oC temperature range. TYPICAL APPLICATION CIRCUIT
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
(c) Copyright 2006 Sipex Corporation
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PINOUT DIAGRAMS
1 2 3 8 RSTB 7 WDI
V1 V2 MRIB
SP6330 8 Pin TSOT
V1 V2
1 2 3
SP6332 8 Pin TSOT
8 RSTB 7 WDI
V1 V2
1 2 3
SP6334 8 Pin TSOT
8 RST 7 WDI 6 GND 5
6 GND MRIB 5
6 GND MRIB 5
V3 4
V4
V3 4
V4
V3 4
V4
Open Drain RESET
CMOS RESET
CMOS RESET
PART NUMBER SP6330 SP6332 SP6334
V1
V2
V3
V4
Reset OD Active Low CMOS Active Low CMOS Active High
MRIB
WDI
Feature and Pinout Diagram
Representative Samples Available
Sipex Product
SP6330 SP6330 SP6330 SP6332
Product Description
Quad Supervisor Open Drain low Quad Supervisor Open Drain low Quad Supervisor Open Drain low Quad Supervisor CMOS low
Package
8 Pin TSOT 8 Pin TSOT 8 Pin TSOT 8 Pin TSOT
V1
(Volts)
V2
(Volts)
V3
(Volts)
V4
(Volts)
Reset
(ms)
Ordering #
SP6330EK1-L-W-G-C SP6330EK1-L-X-J-C SP6330EK1-L-Z-J-C SP6330EK1-L-V-G-C
2.925 3.075 4.625 2.625
1.575 2.313 2.313 1.575
0.5 0.5 0.5 0.5
0.5 0.5 0.5 0.5
200 200 200 200
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device.
Terminal Voltage (with respect to GND) V1, V2..................................................... -0.3 to +6V Open-Drain RSTB.......................................-0.3 to +6V CMOS RST, RSTB, ..................... -0.3 to (V1+0.3V) Input Current/Output Current..................................,,........................20mA V3, V4, MRIB, WDI........................-0.3 to (V1+0.3V)
Operating Temperature Range...............................................-40Cto +85 C Storage Temperature Range...............................................-65C to 150C Thermal Resistance OJA.............................134C/W
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SP6330/32/34 Quad Power Supervisory Circuit Family
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ELECTRICAL CHARACTERISTICS
PARAMETER
Operating Voltage Range Supply Current
MIN
0.9
TYP
MAX
5.5
UNITS
V uA
CONDITIONS
TA = -40C to +85C V1 < 5.5V, V2 < 3.60V, all I/O pins open V1 < 3.6V, V2 < 2.75V, all I/O pins open Z (valid for V1 falling) Y (valid for V1 falling) X (valid for V1 falling) W (valid for V1 falling) V (valid for V1 falling) U (valid for V1 falling) T (valid for V1 falling) S (valid for V1 falling) R (valid for V1 falling) J (valid for V2 falling) I (valid for V2 falling) H (valid for V2 falling) G (valid for V2 falling) F (valid for V2 falling) E (valid for V2 falling) D (valid for V2 falling) C (valid for V2 falling) B (valid for V2 falling) A (valid for V2 falling)
V1 =1.6V to 5.5V; TA = -40C to +85C; unless otherwise noted. Typical values are at TA =+25C
20 15 4.532 4.287 3.013 2.866 2.572 2.273 2.146 1.636 1.548 2.266 2.144 1.631 1.543 1.360 1.286 1.087 1.029 0.816 0.772 4.625 4.375 3.075 2.925 2.625 2.320 2.190 1.670 1.580 2.313 2.188 1.665 1.575 1.388 1.313 1.110 1.050 0.833 0.788 0.06 0.04 0.65 0.5 50 50 37 74 148 296 50 100 200 400
30 25 4.718 4.463 3.137 2.984 2.678 2.367 2.234 1.704 1.612 2.360 2.232 1.698 1.607 1.416 1.340 1.133 1.071 0.850 0.804
V1 Reset Threshold
V
V2 Reset Threshold
V
Threshold 1 Tempco Threshold 2 Tempco Threshold 1 Hysteresis Threshold 2 Hysteresis V1 to RST/RSTB Delay V2 to RST/RSTB Delay Reset Timeout Period (T1) Reset Timeout Period (T2) Reset Timeout Period (T3) Reset Timeout Period (T4)
Nov20-06 Rev M
mV/C mV/C % % us us 63 126 252 504 ms ms ms ms reference to Vth1 typical reference to Vth2 typical V1 = Vth1 to (Vth1-0.1V), Vth1 = 3.075 V2 = Vth2 to (Vth2-0.1V), Vth2 = 1.575 TOPT-1 TOPT-2 TOPT-3 TOPT-4
(c) Copyright 2006 Sipex Corporation
SP6330/32/34 Quad Power Supervisory Circuit Family
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ELECTRICAL CHARACTERISTICS
PARAMETER
MIN
TYP
500 1.5 500 1.5
MAX
510 50
UNITS
CONDITIONS
V1 =1.6V to 5.5V; TA = -40C to +85C; unless otherwise noted. Typical values are at TA =+25C
V3 RESET COMPARATOR INPUT V3 Input Threshold 490 V3 Input Current -50 V3 Threshold Hysteresis V4 RESET COMPARATOR INPUT V4 Input Threshold 490 -50 V4 Input Current V4 Threshold Hysteresis MRIB - MANUAL RESET INPUT MRIB Input Threshold MRIB Input 0.8*V1 Threshold MRIB Minimum 1 Input Pulse Width MRIB Glitch Rejection MRIB to RST/RSTB Delay MRIB Pull-Up 30 Resistance WDI - WATCHDOG INPUT Watchdog Timeout 1.3 Period WDI Pulse Width 0.1 WDI Input Threshold WDI Input 0.8*V1 Threshold WDI Input Current -500 RESET OUTPUTS RST / RSTB RSTB (CMOS or OD) RSTB (CMOS) RST (CMOS) RST (CMOS) RSTB Output OD Leakage Current 0.8*V1 0.8*V1
mV nA mV
TA = +25C
510 50
mV nA mV
TA = +25C
0.2*V1
V V us
Vil Vih
150 100 55 85
ns ns k
1.6
1.9
sec us
0.2*V1
V V
Vil Vih WDI = 0.0V or V1 V1 = Vth1 - 0.1V, Isink = 1mA, output asserted V1 = Vth1 + 0.1V, Isource = 1mA, output not asserted V1 = Vth1 - 0.1V, Isource = 1mA, output asserted V1 = Vth1 + 0.1V, V2 > Vth2, V3 > 0.5, V4 > 0.5, Isource = 1mA, output not asserted TA = +25C
500 0.2*V1
nA V V V
0.2*V1 2
V nA
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PIN DESCRIPTION
Pin # 1 2 3 4 5 6
Name V1 V2 MRIB V3 V4 GND
Description First supply voltage input. Also powers internal circuitry. Trip threshold voltage internally set. Second supply voltage input. Trip threshold voltage internally set. Manual Reset Input pin. Active low. It has an internal pull-up resistor. Reset asserted when MRIB is pulled low and is kept asserted for 200ms after MRIB is released or pulled high. Leave open if not used. Input for the third supply voltage. Trip threshold is 0.5V. Input for the fourth supply voltage. Trip threshold is 0.5V. Common ground reference pin. Watch-Dog Input pin. When no transition is detected at the WDI pin for the duration of WDI timeout period, reset is asserted. Leave open if not used. RST/RSTB output is used to signal watchdog timeout overflow. RST/RSTB output pulses high/low (depending on the active reset polarity) for the reset timeout period after each watchdog timeout overflow. The watchdog timer clears whenever the reset is asserted or manual reset is asserted or a transition is observed at WDI pin. Watchdog timer functionality can be disabled in parts by leaving this input floating. Reset output. Open-Drain or CMOS, active high or low. Reset is asserted when any of the four supply inputs is below its trip threshold. It stays asserted for 200 ms (typical / default) after the last supply input traverses its trip threshold. Reset is guaranteed to be in the correct state for V1>0.9V. RST/RSTB asserts when V1 or V2 or V3 or V4 drop below their corresponding reset thresholds, or MRIB is pulled "LOW" or the watchdog timer triggers a reset (devices without WDOB). RST/RSTB remains asserted for the reset timeout period after V1 and V2 and V3 and V4 exceed their corresponding reset thresholds or MRIB goes "LOW" to "HIGH". Open-drain outputs require an external pull-up resistor. CMOS outputs are referenced to V1.
7
WDI
8
RST/RSTB
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SP6330/32/34 Quad Power Supervisory Circuit Family
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THEORY OF OPERATION
V1 V2 V3 V4 WDI
WDI LOGIC
OSC
Bandgap Ref 1.25V CONTROL LOGIC 0.5V
RSTB (RST)
GND
MRIB
Block Diagram
The SP6330, SP6332, and SP6334 include a low-voltage precision bandgap reference, four precision comparators, an oscillator, a digital counter chain, a logic control block, trimmed resistor divider chains and additional supporting circuitry. The family is designed to supervise up to 4 independent supply voltages. V1 and V2 supply inputs have their resistor dividers on the chip. Their trip thresholds are factory trimmed. V3 and V4 inputs allow user to customize
two additional supply thresholds to be monitored by means of external resistor dividers. The devices also feature manual reset and watchdog functionalities. As these devices do not have watchdog outputs, the watchdog timer is serviced internally during the watchdog timeout period when WDI is left unconnected. The watchdog functionality can be disabled by leaving the WDI input floating.
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SP6330/32/34 Quad Power Supervisory Circuit Family
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THEORY OF OPERATION
Vth1
V1
Vth2
V2
Vth3=0.5V
V3
Vth4=0.5V
V4 MRIB WDI
Trp Trp Trp Twd TRSTB
Figure 1: Functionality of a SP63XX family member with manual reset and watchdog capabilities but without WDOB output. * V1 > Vth1, V2 > Vth2 , V3 > Vth3 and V4 > Vth4 (all supplies over their corresponding thresholds)---> RSTB is de-asserted after reset timeout period (Trp). * MRIB goes to "LOW" to force "Reset" ----> RSTB is asserted immediately. * WDI does not make any transition during watchdog timeout period (Twd) ---->RSTB is asserted for a duration of reset timeout period (Trp). * One of the supplies drops below its corresponding threshold (in this case V3)---->RSTB is asserted immediately.
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SP6330/32/34 Quad Power Supervisory Circuit Family
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APPLICATION INFORMATION
V1
RSTB
ResetB Timeout Delay
WDI = GND, V1=V2=V3=V4=5V, MRIB = open. Watchdog Timeout Period = 1.52S
V1
RSTB
Watchdog Timeout Period
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SP6330/32/34 Quad Power Supervisory Circuit Family
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APPLICATION INFORMATION
Reset Timeout vs. Temperature
Re se t Ti m eo ut (m S ec )
(400ms Reset)
500 400 300 200 100 0 85 80 70 60 50 40 30 20 10 Deg C 0 -10 -20 -30 -40
ResetTimeout Delay Vs. Temperature
R S T B v s . V 1 (V 2 = G N D ) 5 4.5 4
RSTB (Volts DC)
3 3. 2.5 5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V1 (Vdc)
Reset Good
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SP6330/32/34 Quad Power Supervisory Circuit Family
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APPLICATION INFORMATION
V 1 a n d V 2 G litc h r e je c tio n 250 200
Duration (uSec)
150 100 50 0 0 20
RS TB asser ted above line
40
60
80
100
120
Overdrive (mV)
V1 and V2 Glitch Rejection
V 3 a n d V 4 g litc h re je c tio n
120
Duration (uSec)
100 80 60 40 20 0 0 20 40 60 80 100 120
RS TB asser ted above line
O v e rd riv e (mV)
V3 and V4 Glitch Rejection
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SP6330/32/34 Quad Power Supervisory Circuit Family
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PACKAGE: 8 PIN TSOT
D D/2 e1
8 7 6 5
E/2 E1/2 E1 E A
SIDE VIEW
A2 Seating Plane
1
2
3
4
(L1) e
A1
Pin1 Designator to be within this INDEX AREA (D/2 x E1/2)
TOP VIEW
b
FRONT VIEW
o1
Gauge Plane L2 o L Seating Plane o1
R1 R
c
8 Pin TSOT
SYMBOL
JEDEC MO-193
Variation BA Dimensions in Inches Conversion Factor: 1 Inch = 25.40 mm MIN NOM MAX 0.043 0.000 0.004 0.028 0.036 0.039 0.003 0.008 0.114 BSC 0.110 BSC 0.063 BSC 0.012 0.018 0.024 0.024 REF 0.010 BSC 0 4 8 4 10 12 0.004 0.004 0.010 0.009 0.015 0.026 BSC 0.077 BSC JL Oct3-05 / Rev A
Dimensions in Millimeters: Controlling Dimension MIN 0.00 0.70 0.08 NOM 0.90 2.90 BSC 2.80 BSC 1.60 BSC 0.45 0.60 REF 0.25 BSC 4 10 0.65 BSC 1.95 BSC Date/Rev: MAX 1.10 0.10 1.00 0.20
A A1 A2 c D E E1 L L1 L2 O O1 R R1
0.30
0.60
b e e1 SIPEX Pkg Signoff
0 4 0.10 0.10 0.22
8 12 0.25 0.38
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SP6330/32/34 Quad Power Supervisory Circuit Family
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Part Naming Nomenclature
SP63NN - Th1 - Th2 - TOPT
{
Example: AZJD means: SP6330 in TSOT-8 lead package V1 Threshold is 4.625V V2 Threshold is 2.313V Reset Timeout is 400ms
T1 A -- 50 ms T2 B -- 100 ms T3 C -- 200 ms T4 D -- 400 ms A -- 0.788 V B -- 0.833 V C -- 1.050 V D -- 1.110 V E -- 1.313 V F -- 1.388 V G -- 1.575 V H -- 1.665 V I -- 2.188 V J -- 2.313 V
AZJD Pin 1
A 30 -- Quad Sp, MR, WDI, OD RSTB B 31 -- Quad Sp, OD RSTB C 32 -- Quad Sp, MR, WDI, CMOS RSTB D 33 -- Quad Sp, CMOS RSTB E 34 -- Quad Sp, MR, WDI, CMOS RST F 35 -- Quad Sp, CMOS RST G 36 -- Triple Sp, WDI, PF, OD RSTB H 37 -- Triple Sp, WDI, PF, CMOS RSTB I 38 -- Triple Sp, WDI, PF, CMOS RST J 39 -- Triple Sp, MR, WDI, OD RSTB - WDOB K 40 -- Dual Sp, WDI, OD RSTB - WDOB L 41 -- Triple Sp, WDI, PF, CMOS RSTB - WDOB M 42 -- Dual Sp, WDI, CMOS RSTB - WDOB
Nov20-06 Rev M SP6330/32/34 Quad Power Supervisory Circuit Family
{ {
Z -- 4.625 V Y -- 4.375 V X -- 3.075 V W -- 2.925 V V -- 2.625 V U -- 2.320 V T -- 2.190 V S -- 1.670 V R -- 1.580 V
(c) Copyright 2006 Sipex Corporation
12
ORDERING INFORMATION
Model Package Types
Temperature Range
SP6330EK1-L-X-X-X...........................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6330EK1-L-X-X-X/TR......................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6332EK1-L-X-X-X............................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6332EK1-L-X-X-X/TR......................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6334EK1-L-X-X-X............................................-40C to +85C.................................Lead Free 8-Pin TSOT SP6334EK1-L-X-X-X/TR......................................-40C to +85C.................................Lead Free 8-Pin TSOT Available in lead free packaging only. /TR = Tape and Reel Pack quantity 2,500 forTSOT-8 Contact Factory for availability of particular voltage threshold and reset timeout options. Note that the Ordering Information denoting those options corresponds to the Part Naming Nomenclature shown on the previous page. Ordering example: SP6330EK1-L-W-G-C/TR == W -- 2.925V for Voltage Threshold 1; G -- 1.575V for Voltage Threshold 2; and C -- 200ms reset timeout.
Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Nov20-06 Rev M
SP6330/32/34 Quad Power Supervisory Circuit Family
(c) Copyright 2006 Sipex Corporation
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